Field
This invention relates in general to electrostatic discharge (ESD) protection for semiconductor devices and more specifically to ESD protection circuits with PFET feedback.
Description of the Related Art
An integrated circuit may be subjected to a damaging Electrostatic Discharge (ESD) event in the manufacturing process, during assembly and testing, or in the ultimate system application. In conventional integrated circuit (IC) ESD protection schemes, special ESD protection circuits known as clamp circuits are often used to shunt ESD current between the power supply rails and thereby protect internal elements from damage. A type of ESD clamp circuit, known as an active Metal Oxide Semiconductor Field Effect Transistor (MOSFET) clamp circuit, typically comprises three parts: a trigger circuit, a delay stage, and a large MOSFET transistor. The trigger circuit is designed to respond to an applied ESD event but remains inactive during normal operation of the IC. The delay stage is used to buffer and prolong the trigger output in order to drive the gate terminal of the large MOSFET transistor. The large MOSFET transistor, connected between the two power supply rails, acts as the primary ESD current dissipation device in the clamp circuit. Active MOSFET clamp circuits typically rely on only MOSFET action to absorb ESD events, and since the peak current in an ESD event is on the order of amperes, large MOSFET transistor sizes are required. Active MOSFET clamp circuits may be employed in networks distributed along the power buses to provide robust and consistent ESD protection for all the Input/Output (I/O) pads in the IC.
The use of the same reference symbols in different drawings indicates identical items unless otherwise noted. The figures are not necessarily drawn to scale.